In recent years, consumers have demanded that a semiconductor device have a higher packing density and higher performance, and those demands have increased the number of MOS transistors formed on a semiconductor substrate.
A general MOS transistor has impurity regions serving as a source and a drain (hereinafter referred to as “source and drain regions” or a “source/drain region” in a representative way), a channel region, and an extension region disposed at each end of the channel region. Such a MOS transistor is formed, for example, by the method described below.
A gate insulation film and a gate electrode are formed on a silicon semiconductor substrate. Extension regions are formed by ion-implanting impurities into the semiconductor substrate with the gate electrode being used as a mask. Sidewall spacers are formed on both sides of the gate electrode. The source and drain regions are formed by ion-implanting impurities into the semiconductor substrate at a higher concentration up to a depth deeper than the extension regions with the gate electrode and the sidewall spacers being used as masks. Heat treatment (thermal processing) is performed to activate the impurities having been introduced to the semiconductor substrate. A MOS transistor having the extension regions is completed in this way.
As described above, a heat treatment operation for activating the impurities (hereinafter also referred to as an “activation heat treatment” operation) is performed in a process of manufacturing the MOS transistor. In the heat treatment operation, the impurities implanted to the source and drain regions are diffused into the interior of the semiconductor substrate under the gate electrode such that the spacing between the source and the drain (hereinafter also referred to as the “channel length”) is shortened. The shorter spacing between the source and the drain gives rise to the so-called channel shortening effect with which a threshold voltage is reduced. For that reason, the activation heat treatment is performed in a short time by using, e.g., the RTA (Rapid Thermal Annealing) process. Further, the thickness of each sidewall spacer is set to a value that is suitable to minimize the shorter channel effect caused by the diffusion of the impurities.
It is known that the diffusion distance of the impurities during the heat treatment operation is related to the impurity concentration. In view of such a point, a MOS transistor has been proposed in which the impurity concentration in the source is set higher than that in the drain and the thickness of the sidewall spacer on the same side as the source is increased to suppress an overlap between the source and the gate electrode, as disclosed in, e.g., Japanese Laid-Open Patent Publication No. 2005-5372.